SH7144 Datasheet, PDF (756/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Item
Table 8.6 State Counts
Needed for Execution
State
8.4.3 DTC Use
Example
Page
122
123
Figure 9.1 BSC Block 126
Diagram
Revisions (See Manual for Details)
Name amended.
Longword data read S_L → Longword data write S_L
Description amended.
6. When DTCRA is 0 after the 128 data transfers have
ended, the RDRF flag is held at 1, the corresponding bit
in DTER is cleared to 0, and an RXI interrupt request is
sent to the CPU. The interrupt handling routine should
perform completion processing.
Figure amended.
Table 9.2 Address Map 129
Figure 10.3 (1) Round 166
Robin Mode
11.1 Features
191
On-chip memory
control unit
RAMER
Address amended.
• On-chip ROM disabled mode
H’02000000 to H’FFFF7FFF → H’01000000 to H’FFFF7FFF
Figure amended.
Transfer on channel 0
Initial priority setting _{CH0 > CH1 > CH2 > CH3}
Channel 0 is given the lowest
priority.
Priority after transfer
CH1 > CH2 > CH3 > CH0
Features added.
• A total of six-phase waveform output, which includes
complementary PWM output, and positive and negative
phases of reset PWM output by interlocking operation of
channels 3 and 4, is possible.
• AC synchronous motor (brushless DC motor) drive mode
using complementary PWM output and reset PWM output
is settable by interlocking operation of channels 0, 3, and
4, and the selection of two types of waveform outputs
(chopping and level) is possible.
Rev. 2.0, 09/02, page 716 of 732