SH7144 Datasheet, PDF (466/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 14.5 Description of IRIC
Bit1
IRIC
0
1
Description
While in transfer-wait state or during a transfer
[Clearing condition]
(1) Writing of 0 to this bit after reading IRIC = 1
(2) When reading from/writing to ICDR by DTC
(3) When the TDRE flag is cleared to 0
An interrupt is generated.
[Setting conditions]
• I²C bus format in master mode
(1) When the start condition is detected from the bus line’s state after the start
condition has been set (i.e., when the TDRE flag has been set to 1 for
transmission of the first frame).
(2) When WAIT = 1, a wait is inserted between the data bits and the acknowledge bit.
(3) When the transfer of data has been completed (i.e., when the TDRE or RDRF flag
has been set to 1).
(4) When transfer has failed because of a bus conflict.
(5) When the ACKE bit is 1 and WAIT = 0, and 1 is received as an acknowledge bit
(i.e., when the ACKB bit is set to 1).
• I²C bus format in the slave mode
(1) When a slave address (SVA or SVAX) has been matched (i.e., when the AAS or
AASX flags have been set to 1), or when the re-transmission condition is satisfied
or the subsequent data transfer has been completed. (i.e., when the TDRE or
RDRF flag is set to 1)
(2) When the general call address has been detected (i.e., when the ADZ flag has
been set to 1) or when the re-transmission condition is satisfied or the subsequent
data transfer has been completed. (i.e., when the TDRE or RDRF flag is set to 1)
(3) When the ACKE bit is 1 and WAIT = 0, and 1 is received as an acknowledge bit
(i.e., when the ACKB bit is set to 1)
(4) When the stop condition is detected while the STOPIM bit in SCRX is set to 0
(i.e., when the SCRX STOPIM bit is set to 0, and the STOP or the ESTP flag is
set to 1)
• Clock synchronized serial format
(1) When the transfer of data has been completed (i.e., when the TDRE or the RDRF
flag has been set to 1)
(2) When the start condition has been detected while the interface is set for serial
format
Cases other than the above in which TDRE or RDRF is set to 1.
Rev. 2.0, 09/02, page 426 of 732