SH7144 Datasheet, PDF (642/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

that is connected to TDI and TDO in bypass mode. Except for SDBPR, all the registers can be
accessed by the CPU.
Table 22.2 shows the kinds of serial transfer that can be used with each of the H-UDI’s registers.
Table 22.2 Serial Transfer Characteristics of H-UDI Registers
Register
SDIR
SDSR
SDDRH
SDDRL
SDBPR
Serial Input
Possible
Not possible
Possible
Possible
Possible
Serial Output
Not possible
Possible
Possible
Possible
Possible
22.3.1 Instruction Register (SDIR)
The instruction register (SDIR) is a 16-bit register that can be read, but not written to, by the CPU.
H-UDI instructions can be transferred to SDIR from TDI by serial input. SDIR can be initialized
by the TRST signal, but is not initialized in software standby mode.
Instructions transferred to SDIR must be 4 bits in length. If an instruction exceeding 4 bits is input,
the last 4 bits of the serial data will be stored in SDIR.
Bit
Bit
Name
15
TS3
14
TS2
13
TS1
12
TS0
11 to 0 
Initial R/W
value
1
R
1
R
1
R
1
R
All 0 R
Description
Test set bit
0xxx: setting prohibited
100x: setting prohibited
1010: H-UDI interrupt
1011: setting prohibited
110x: setting prohibited
1110: setting prohibited
1111: BYPASS mode
Reserved
These bits are always read as 0, and should only be
written with 0.
Rev. 2.0, 09/02, page 602 of 732