SH7144 Datasheet, PDF (23/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

23.5.1 Initialization .........................................................................................................619
23.5.2 Operation in Software Standby Mode..................................................................619
23.5.3 Setting the PA15/CK pin......................................................................................619
23.5.4 Pin States..............................................................................................................619
23.5.5 AUD Start-up Sequence.......................................................................................620
Section 24 Power-Down Modes ....................................................................... 621
24.1 Input/Output Pins ..............................................................................................................623
24.2 Register Descriptions ........................................................................................................623
24.2.1 Standby Control Register (SBYCR) ....................................................................623
24.2.2 System Control Register (SYSCR) ......................................................................625
24.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2).................626
24.3 Operation...........................................................................................................................628
24.3.1 Sleep Mode ..........................................................................................................628
24.3.2 Software Standby Mode.......................................................................................629
24.3.3 Module Standby Mode.........................................................................................631
24.4 Usage Notes ......................................................................................................................632
24.4.1 I/O Port Status......................................................................................................632
24.4.2 Current Consumption during Oscillation Stabilization Wait Period ....................632
24.4.3 On-Chip Peripheral Module Interrupt..................................................................632
24.4.4 Writing to MSTCR1 and MSTCR2 .....................................................................632
24.4.5 DMAC, DTC, or AUD Operation in Sleep Mode................................................632
Section 25 List of Registers .............................................................................. 633
25.1 Register Address Table (In the Order from Lower Addresses).........................................633
25.2 Register Bit List ................................................................................................................645
25.3 Register States in Each Operating Mode...........................................................................658
Section 26 Electrical Characteristics ................................................................ 665
26.1 Absolute Maximum Ratings .............................................................................................665
26.2 DC Characteristics ............................................................................................................666
26.3 AC Characteristics ............................................................................................................669
26.3.1 Test conditions for the AC characteristics ...........................................................669
26.3.2 Clock timing ........................................................................................................670
26.3.3 Control Signal Timing .........................................................................................672
26.3.4 Bus Timing ..........................................................................................................675
26.3.5 Direct Memory Access Controller (DMAC) Timing ...........................................679
26.3.6 Multi-Function Timer Pulse Unit (MTU)Timing.................................................681
26.3.7 I/O Port Timing....................................................................................................682
26.3.8 Watchdog Timer (WDT)Timing ..........................................................................683
26.3.9 Serial Communication Interface (SCI)Timing.....................................................684
26.3.10 I²C Bus Interface Timing .....................................................................................686
26.3.11 Output Enable (POE) Timing ..............................................................................687
Rev. 2.0, 09/02, page xxi of xxxviii