SH7144 Datasheet, PDF (673/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Section 25 List of Registers
This section gives information on internal I/O registers. The contents of this section are as follows:
1. Register Address Table (in the order from a lower address)
• Registers are listed in the order from lower allocated addresses.
• As for reserved addresses, the register name column is indicated with . Do not access
reserved addresses.
• As for 16- or 32-bit address, the MSB addresses are shown.
• The list is classified according to module names.
2. Register Bit Table
• Bit configurations are shown in the order of the register address table.
• As for reserved bits, the bit name column is indicated with .
• As for the blank column of the bit names, the whole register is allocated to the counter or data.
• As for 16- or 32-bit registers, bits are indicated from the MSB.
3. Register State in Each Operating Mode
• Register states are listed in the order of the register address table.
• Register states in the basic operating mode are shown. As for modules including their specific
states such as reset, see the sections of those modules.
25.1 Register Address Table (In the Order from Lower Addresses)
Access sizes are indicated with the number of bits. Access states are indicated with the number of
specified reference clock states. These values are those at 8-bit access (B), 16-bit access (W), or
32-bit access (L).
Note: Access to undefined or reserved addresses is prohibited. Correct operation cannot be
guaranteed if these addresses are accessed.
Rev. 2.0, 09/02, page 633 of 732