SH7144 Datasheet, PDF (137/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

UBARH/UBARL
UBAMRH/UBAMRL
Internal address
bits 31–0
32
32
32
32
32
CP1 CP0
CPU cycle
DMAC/DTC cycle
Instruction fetch
ID1 ID0
Data access
Read cycle
RW1 RW0
Write cycle
SZ1 SZ0
User
break
interrupt
Byte size
Word size
Longword size
UBID
Figure 7.2 Break Condition Determination Method
Rev. 2.0, 09/02, page 97 of 732