SH7144 Datasheet, PDF (26/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Figure 8.8 Memory Mapping in Block Transfer Mode............................................................... 119
Figure 8.9 Chain Transfer........................................................................................................... 120
Figure 8.10 DTC Operation Timing Example (Normal Mode) .................................................. 121
Section 9 Bus State Controller (BSC)
Figure 9.1 BSC Block Diagram.................................................................................................. 126
Figure 9.2 Address Format ......................................................................................................... 128
Figure 9.3 Basic Timing of External Space Access.................................................................... 138
Figure 9.4 Wait State Timing of External Space Access (Software Wait Only) ........................ 139
Figure 9.5 Wait State Timing of External Space Access
(Two Software Wait States + WAIT Signal Wait State)............................................ 140
Figure 9.6 CS Assert Period Extension Function ....................................................................... 141
Figure 9.7 Example of Idle Cycle Insertion................................................................................ 143
Figure 9.8 Example of Idle Cycle Insertion at Same Space Consecutive Access....................... 144
Figure 9.9 Bus Mastership Release Procedure............................................................................ 145
Figure 9.10 Example of 8-bit Data Bus Width ROM Connection .............................................. 145
Figure 9.11 Example of 16-bit Data Bus Width ROM Connection ............................................ 146
Figure 9.12 Example of 32-bit Data Bus Width ROM Connection (only for SH7145).............. 146
Figure 9.13 Example of 8-bit Data Bus Width SRAM Connection............................................ 146
Figure 9.14 Example of 16-bit Data Bus Width SRAM Connection.......................................... 147
Figure 9.15 Example of 32-bit Data Bus Width SRAM Connection (only for SH7145) ........... 147
Figure 9.16 One Bus Cycle......................................................................................................... 148
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 DMAC Block Diagram............................................................................................ 150
Figure 10.2 DMAC Transfer Flowchart ..................................................................................... 162
Figure 10.3 (1) Round Robin Mode............................................................................................ 166
Figure 10.3 (2) Example of Changes in Priority in Round Robin Mode .................................... 167
Figure 10.4 Data Flow in Single Address Mode......................................................................... 169
Figure 10.5 Example of DMA Transfer Timing in the Single Address Mode............................ 169
Figure 10.6 Direct Address Operation during Dual Address Mode............................................ 170
Figure 10.7 Example of Direct Address Transfer Timing in Dual Address Mode ..................... 171
Figure 10.8 Dual Address Mode and Indirect Address Operation
(When External Memory Space is 16 bits) .............................................................. 172
Figure 10.9 Dual Address Mode and Indirect Address Transfer Timing Example
(External Memory Space to External Memory Space, 16-bit width) ....................... 173
Figure 10.10 Dual Address Mode and Indirect Address Transfer Timing Example
(On-chip Memory Space to On-chip Memory Space) ........................................... 174
Figure 10.11 DMA Transfer Example in the Cycle-Steal Mode ................................................ 175
Figure 10.12 DMA Transfer Example in the Burst Mode .......................................................... 175
Figure 10.13 Bus Handling when Multiple Channels Are Operating ......................................... 177
Figure 10.14 Cycle Steal, Dual Address and Level Detection (Fastest Operation) .................... 180
Figure 10.15 Cycle Steal, Dual Address and Level Detection (Normal Operation) ................... 180
Figure 10.16 Cycle Steal, Single Address and Level Detection (Fastest Operation).................. 180
Rev. 2.0, 09/02, page xxiv of xxxviii