SH7144 Datasheet, PDF (221/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

CK
DRAK
Bus
cycle
DACK
CPU
CPU
CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) CPU DMAC(R)
Figure 10.18 Burst Mode, Dual Address and Level Detection (Fastest Operation)
CK
DRAK
Bus
cycle
DACK
CPU
CPU
CPU
DMAC(R)
DMAC(W)
DMAC(R) DMAC(W)
DMAC(R)
Figure 10.19 Burst Mode, Dual Address and Level Detection (Normal Operation)
1st sampling
2nd sampling
CK
3rd sampling
4th sampling
DRAK
Bus
cycle
CPU(1)
CPU(2) CPU(3) Dummy
DACK
DMAC
DMAC
DMAC
CPU(4) Dummy
Figure 10.20 Burst Mode, Single Address and Level Detection (Fastest Operation)
CK
DRAK
Bus
cycle
DACK
CPU
CPU
CPU
Dummy
DMAC
DMAC
DMAC
Figure 10.21 Burst Mode, Single Address and Level Detection (Normal Operation)
Rev. 2.0, 09/02, page 181 of 732