SH7144 Datasheet, PDF (475/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit
Name
2
Initial Value R/W
0
R
1 ICDRF0 0
R
0 STOPIM 0
R/W
Note: * Set this bit to 1.
Description
This bit is reserved and always returns 0 when read,
and should only be written with 0.
This bit indicates whether or not ICDR contains valid
received data.
0: Indicates that ICDR does not contain valid received
data.
1: Indicates that ICDR contains valid received data.
Stop-condition-detected-interrupt mask
This bit enables/disables the issuing of stop-condition-
detected interrupt requests in the I²C bus format in the
slave mode.
0: This setting enables the stop-condition-detected
interrupt requests in the I²C bus format in the slave
mode.
1: This setting disables the stop-condition-detected
interrupt requests in the I²C bus format in the slave
mode.
14.4 Operation
14.4.1 I²C Bus Data Formats
The I²C bus interface is capable of transferring data in either the serial format or the I²C bus
format. The I²C bus format is referred to as an addressing format. The transfer of data in this
addressing format includes the transfer of acknowledge bits. This is shown in figures 14.3, (a) and
(b). The first frame after the start condition always consists of 8 bits.
The serial format is referred to as a ‘non-addressing format’. The transfer of data in this non-
addressing format does not include the transfer of an acknowledge bit. This is shown in figure
14.4. The I²C bus timing is shown in figure 14.5.
The symbols used in figures 14.3 to 14.5 are described in table 14.7.
Rev. 2.0, 09/02, page 435 of 732