SH7144 Datasheet, PDF (191/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

10.2 Input/Output Pins
Table 10.1 shows the DMAC pins.
Table 10.1 DMAC Pin Configuration
Channel Name
Symbol I/O
0
DMA transfer request DREQ0 I
DMA transfer request DACK0 O
acknowledge
DREQ0 acceptance
confirmation
DRAK0 O
1
DMA transfer request DREQ1 I
DMA transfer request DACK1 O
acknowledge
DREQ1 acceptance
confirmation
DRAK1 O
Function
DMA transfer request input from
external device to channel 0
DMA transfer strobe output from
channel 0 to external device
Sampling receive acknowledge output
for DMA transfer request input from
external source
DMA transfer request input from
external device to channel 1
DMA transfer strobe output from
channel 1 to external device
Sampling receive acknowledge output
for DMA transfer request input from
external source
10.3 Register Descriptions
DMAC has a total of 17 registers. Each channel has four control registers. One other control
register is shared by all channels. For register address and their states in each operating mode,
refer to section25, List of Registers.
• DMA source address register_0 (SAR_0)
• DMA destination address register_0 (DAR_0)
• DMA transfer count register_0 (DMATCR_0)
• DMA channel control register_0 (CHCR_0)
• DMA source address register_1 (SAR_1)
• DMA destination address register_1 (DAR_1)
• DMA transfer count register_1 (DMATCR_1)
• DMA channel control register_1 (CHCR_1)
• DMA source address register_2 (SAR_2)
• DMA destination address register_2 (DAR_2)
• DMA transfer count register_2 (DMATCR_2)
• DMA channel control register_2 (CHCR_2)
• DMA source address register_3 (SAR_3)
Rev. 2.0, 09/02, page 151 of 732