SH7144 Datasheet, PDF (16/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

11.3.3 Timer I/O Control Register (TIOR) ..................................................................... 203
11.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 221
11.3.5 Timer Status Register (TSR)................................................................................ 223
11.3.6 Timer Counter (TCNT)........................................................................................ 226
11.3.7 Timer General Register (TGR) ............................................................................ 226
11.3.8 Timer Start Register (TSTR)................................................................................ 227
11.3.9 Timer Synchronous Register (TSYR).................................................................. 227
11.3.10 Timer Output Master Enable Register (TOER) ................................................... 229
11.3.11 Timer Output Control Register (TOCR) .............................................................. 230
11.3.12 Timer Gate Control Register (TGCR).................................................................. 231
11.3.13 Timer Subcounter (TCNTS) ................................................................................ 233
11.3.14 Timer Dead Time Data Register (TDDR)............................................................ 233
11.3.15 Timer Period Data Register (TCDR) ................................................................... 234
11.3.16 Timer Period Buffer Register (TCBR)................................................................. 234
11.3.17 Bus Master Interface ............................................................................................ 234
11.4 Operation .......................................................................................................................... 235
11.4.1 Basic Functions.................................................................................................... 235
11.4.2 Synchronous Operation........................................................................................ 240
11.4.3 Buffer Operation .................................................................................................. 242
11.4.4 Cascaded Operation ............................................................................................. 245
11.4.5 PWM Modes ........................................................................................................ 247
11.4.6 Phase Counting Mode.......................................................................................... 252
11.4.7 Reset-Synchronized PWM Mode......................................................................... 258
11.4.8 Complementary PWM Mode............................................................................... 261
11.5 Interrupt Sources............................................................................................................... 284
11.5.1 Interrupt Sources and Priorities............................................................................ 284
11.5.2 DTC/DMAC Activation....................................................................................... 286
11.5.3 A/D Converter Activation.................................................................................... 286
11.6 Operation Timing.............................................................................................................. 287
11.6.1 Input/Output Timing ............................................................................................ 287
11.6.2 Interrupt Signal Timing ....................................................................................... 291
11.7 Usage Notes ...................................................................................................................... 294
11.7.1 Module Standby Mode Setting ............................................................................ 294
11.7.2 Input Clock Restrictions ...................................................................................... 294
11.7.3 Caution on Period Setting .................................................................................... 295
11.7.4 Contention between TCNT Write and Clear Operations..................................... 295
11.7.5 Contention between TCNT Write and Increment Operations.............................. 295
11.7.6 Contention between TGR Write and Compare Match ......................................... 296
11.7.7 Contention between Buffer Register Write and Compare Match ........................ 297
11.7.8 Contention between TGR Read and Input Capture.............................................. 298
11.7.9 Contention between TGR Write and Input Capture............................................. 299
11.7.10 Contention between Buffer Register Write and Input Capture ............................ 300
11.7.11 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..... 300
Rev. 2.0, 09/02, page xiv of xxxviii