SH7144 Datasheet, PDF (585/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Register Bit
PECRL2 13
PECRL2 12
PECRL2 11
PECRL2 10
PECRL2 9
PECRL2 8
PECRL2 7
PECRL2 6
PECRL2 5
PECRL2 4
Initial
Bit Name Value R/W
PE6MD1 0
R/W
PE6MD0 0
R/W
PE5MD1 0
R/W
PE5MD0 0
R/W
PE4MD1 0
R/W
PE4MD0 0
R/W
PE3MD1 0
R/W
PE3MD0 0
R/W
PE2MD1 0
R/W
PE2MD0 0
R/W
Description
PE6 Mode
Select the function of the PE6/TIOC2A/SCK3
pin.
00: PE6 I/O (port)
01: TIOC2A I/O (MTU)
10: SCK3 I/O (SCI)
11: Setting prohibited
PE5 Mode
Select the function of the PE5/TIOC1B/TXD3
pin.
00: PE5 I/O (port)
01: TIOC1B I/O (MTU)
10: TXD3 output (SCI)
11: Setting prohibited
PE4 Mode
Select the function of the
PE4/TIOC1A/RXD3/TCK pin. Fixed to TCK input
when using E10A (in DBGMD=H).*
00: PE4 I/O (port)
01: TIOC1A I/O (MTU)
10: RXD3 input (SCI)
11: Setting prohibited
PE3 Mode
Select the function of the
PE3/TIOC0D/DRAK1/TDO pin. Fixed to TDO
output when using E10A (in DBGMD=H).*
00: PE3 I/O (port)
01: TIOC0D I/O (MTU)
10: DRAK1 output (DMAC)
11: Setting prohibited
PE2 Mode
Select the function of the
PE2/TIOC0C/DREQ1/TDI pin. Fixed to TDI input
when using E10A (in DBGMD=H).*
00: PE2 I/O (port)
01: TIOC0C I/O (MTU)
10: DREQ1 input (DMAC)
11: Setting prohibited
Rev. 2.0, 09/02, page 545 of 732