SH7144 Datasheet, PDF (161/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Note: When the DTCR contains a value equal to or greater than 2, the SWDTE bit is
automatically cleared to 0. When the DTCR is set to 1, the SWDTE bit is again set to 1.
8.3.5 Operation Timing
When register information is located in on-chip RAM, each mode requires 4 cycles for transfer
information reads, and 3 cycles for writes.
φ
Activating
source
DTC
request
Address
Vector
read
Transfer information
read
RW
Data
Transfer
transfer information write
Figure 8.10 DTC Operation Timing Example (Normal Mode)
8.3.6 DTC Execution State Counts
Table 8.5 shows the execution state for one DTC data transfer. Furthermore, table 8.6 shows the
state counts needed for execution state.
Table 8.5 Execution State of DTC
Mode
Register
Information
Vector Read I Read/Write J Data Read K
Normal
1
7
1
Repeat
1
7
1
Block transfer 1
7
N
N: block size (default set values of DTCRB)
Data Write L
1
1
N
Internal
Operation M
1
1
1
Rev. 2.0, 09/02, page 121 of 732