SH7144 Datasheet, PDF (413/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

13.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and the effective bit rate B₀ for asynchronous and
clocked synchronous modes. The initial value of BRR is H'FF, and it can be read or written to by
the CPU at all times.
Table 13.2 Relationships between N Setting in BRR and Effective Bit Rate B₀
Mode
Asynchronous mode
(n = 0)
Asynchronous mode
(n = 1 to 3)
Clocked synchronous
mode (n = 0)
Bit Rate
Pφ × 10⁶
B₀ = _{32 × 22n × (N + 1)}
Pφ × 10⁶
B₀ = _{32 × 22n+1 × (N + 1)}
Pφ × 10⁶
B₀ = _{4 × 22n × (N + 1)}
Error
Error (%) =
B₀
B₁
– 1^ × 100
Error (%) =
B₀
B₁
– 1^ × 100
—
Clocked synchronous
Pφ × 10⁶
mode (n = 1 to 3)
B₀ = _{4 × 22n+1 × (N + 1)}
—
Legend:
B₀: Effective bit rate (bit/s) Actual transfer speed according to the register settings
B : Logical bit rate (bit/s) Specified transfer speed of the target system
1
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral clock operating frequency (MHz)
n : Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1
CKS0
n
0
0
0
0
1
1
1
0
2
1
1
3
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N
settings in BRR in clocked synchronous mode. For details, refer to section 13.4.2, Receive Data
Sampling Timing and Reception Margin in Asynchronous Mode. Tables 13.5 and 13.7 show the
maximum bit rates with external clock input.
Rev. 2.0, 09/02, page 373 of 732