SH7144 Datasheet, PDF (565/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Register Bit
Initial
Bit Name Value R/W Description
PACRL2 3
PA1MD1 0
R/W PA1 Mode
PACRL2 2
PA1MD0 0
R/W Select the function of the PA1/TXD0 pin.
00: PA1 I/O (port)
01: TXD0 output (SCI)
10: Setting prohibited
11: Setting prohibited
PACRL2 1
PA0MD1 0
R/W PA0 Mode
PACRL2 0
PA0MD0 0
R/W Select the function of the PA0/RXD0 pin.
00: PA0 I/O (port)
01: RXD0 input (SCI)
10: Setting prohibited
11: Setting prohibited
Notes: 1. F-ZTAT only. Setting prohibited for the mask version.
2. The initial value is 1 in the on-chip ROM enabled/disabled external-expansion mode.
3. The initial value is 1 in the on-chip ROM disabled external-expansion mode.
17.1.3 Port B I/O Register (PBIOR)
The port B I/O register (PBIOR) is a 16-bit readable/writable register that is used to set the pins on
port B as inputs or outputs. Bits PB9IOR to PB0IOR correspond to pins PB9 to PB0 (names of
multiplexed pins are here given as port names and pin numbers alone). PBIOR is enabled when
port B pins are functioning as general-purpose inputs/outputs (PB9 to PB0). In other states,
PBIOR is disabled.
A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an
input pin if the bit is cleared to 0.
Bits 15 to 10 are reserved. These bits are always read as 0 and should only be written with 0.
The initial value of PBIOR is H′0000.
Rev. 2.0, 09/02, page 525 of 732