SH7144 Datasheet, PDF (480/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

14.4.3 Operations in Master Reception
In master-reception mode, the master device outputs the reception clock, receives data, and returns
acknowledgements of reception. The slave device transmits the data. The following description
gives the procedures for and operations of reception in master mode.
1. Clear the TRS bit in ICCR to 0 to change from the transmission mode to the reception mode.
In addition, clear the ACKB bit in ICSR to 0 (setting of the acknowledge bit).
2. When ICDR is read (a dummy read operation), the receiving of data starts; the receive clock is
output in synchronization with the internal clock, and the first datum is then received. To
determine the completion of its reception, clear the IRIC flag in ICCR.
3. The master device sets SDA to low on the 9th cycle of the receive clock and returns the
acknowledge bit. When the reception of one frame of data has been completed, the IRIC flag
in ICCR is set to 1 on the rising edge of the 9th cycle of the receive clock. When the IEIC bit
in ICCR has been set to 1, an interrupt request is generated for the CPU. In this case, if the
internal RDRF flag has been cleared to 0, the internal RDRF flag is set to 1 to continue with
reception. When the reception of the next frame is completed before the ICDR is read to clear
the IRIC flag as in step 4 below, SCL is automatically fixed to its low level in synchronization
with the internal clock.
4. Read ICDR to clear the IRIC flag in ICCR to 0. This clears the RDRF flag to 0.
Data can be continuously received by repeatedly performing steps 3 and 4 above. When receiving
is started by the change from master-transmission to master-reception mode, the internal RDRF
flag is cleared to 0. Initiation of the receiving of the next frame of data is thus automatic. To stop
receiving, the TRS bit must be set to 1 before the reception clock has started up for the next frame.
When stopping a receive operation, set the TRS bit to 1, read ICDR, and then write 0 to the BBSY
and the SCP bits of ICCR. By doing so, the level on SDA is changed from low to high while SCL
is high, and this is the stop condition.
Rev. 2.0, 09/02, page 440 of 732