SH7144 Datasheet, PDF (446/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

13.7 Interrupt Sources
13.7.1 Interrupts in Normal Serial Communication Interface Mode
Table 13.10 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the
DMAC or DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data
transfer is performed by the DMAC or DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DMAC or DTC to perform data transfer. The RDRF flag is cleared to 0
automatically when data transfer is performed by the DMAC or DTC.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Rev. 2.0, 09/02, page 406 of 732