SH7144 Datasheet, PDF (668/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

24.3 Operation
24.3.1 Sleep Mode
Transition to Sleep Mode: If SLEEP instruction is executed while the SSBY bit in SBYCR = 0,
the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the
CPU's internal registers are retained. Peripheral functions except the CPU do not stop.
In sleep mode, data should not be accessed by the DMAC, DTC, or AUD.
Clearing Sleep Mode: Sleep mode is cleared by the conditions below.
• Clearing by the power-on reset
When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven
high after the elapse of the specified reset input period, the CPU starts the reset exception
handling.
When an internal Power-on reset by WDT occurs, sleep mode is also cleared.
• Clearing by the manual reset
When the MRES pin is driven low while the RES pin is high, the CPU shifts to the manual
reset state and thus sleep mode is cleared.
When an internal manual reset by WDT occurs, sleep mode is also cleared.
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