SH7144 Datasheet, PDF (159/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 8.4 Block Transfer Mode Register Functions
Register
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Function
Operation mode
control
Transfer count
Block length
Transfer source
address
Transfer destination
address
Values Written Back upon a Transfer Information Write
DTMR
DTCRA – 1
(Not written back)
(DTS = 0) Increment/ decrement/ fixed
(DTS = 1) DTSAR initial value
(DTS = 0) DTDAR initial value
(DTS = 1) Increment/ decrement/ fixed
DTSAR
or
DTDAR
First block
•
•
Block area
•
Transfer
Nth block
DTDAR
or
DTSAR
Figure 8.8 Memory Mapping in Block Transfer Mode
Chain Transfer: Setting the CHNE bit to 1 enables a number of data transfers to be performed
consecutively in a single activation source. DTSAR, DTDAR, DTMR, DTCRA, and DTCRB can
be set independently.
Figure 8.9 shows the chain transfer.
When activated, the DTC reads the register information start address stored at the vector address,
and then reads the first register information at that start address. After the data transfer, the CHNE
bit will be tested. When it has been set to 1, DTC reads next register information located in a
consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit
is cleared to 0.
Rev. 2.0, 09/02, page 119 of 732