SH7144 Datasheet, PDF (470/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
Bit Name
5 IRTR
4 AASX
Initial
Value
0
R/W
R/(W)*
0
R/(W)*
Description
I²C-bus-interface continuous transfer interrupt-request flag
The IRTR flag indicates that the I²C bus interface has
generated an interrupt for the CPU. The IRIC flag is set to
1 at the same time as the IRTR flag is set to 1.
The IRTR flag is set while the TDRE or RDRF flag is set to
1. The IRTR flag is cleared by reading an existing 1 from
and then writing a 0 to the flag. The IRTR flag is
automatically cleared when the IRIC flag is cleared.
0: Transfer-wait state or during transfer
[Clearing conditions]
(1) Writing of 0 to this bit after reading IRTR = 1
(2) Clearing of the IRIC flag to 0
1: Continuous-transfer state
[Setting conditions]
(1) Setting of the TDRE or RDRF flag to 1 while AASX is 1
in the I²C bus interface in the slave mode.
(2) Setting of the TDRE or RDRF flag to 1 when not in the
I²C bus interface in the slave mode.
Second slave-address detection flag
For the I²C bus interface in the slave mode, the AASX flag
is set to 1 when the first frame after the start condition
matches bits SVAX6 to SVAX0 of SARX.
To clear the AASX flag, read a 1 from and then write a 0 to
it. When the start condition is detected, the flag is
automatically cleared.
0: The second slave address of this device has not been
detected.
[Clearing conditions]
(1) Writing of 0 to this bit after reading AASX = 1
(2) Detection of the start condition.
(3) Entering master mode
1: This device’s second slave address has been detected
[Setting condition]
(1) Detection of the second slave address in the slave
receive mode while FSX = 0.
Rev. 2.0, 09/02, page 430 of 732