SH7144 Datasheet, PDF (21/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

17.1.11 High-Current Port Control Register (PPCR)........................................................550
17.2 Precautions for Use ...........................................................................................................550
Section 18 I/O Ports .......................................................................................... 553
18.1 Port A ................................................................................................................................553
18.1.1 Register Descriptions ...........................................................................................555
18.1.2 Port A Data Registers H and L (PADRH and PADRL).......................................555
18.2 Port B ................................................................................................................................557
18.2.1 Register Descriptions ...........................................................................................557
18.2.2 Port B Data Register (PBDR) ..............................................................................557
18.3 Port C ................................................................................................................................559
18.3.1 Register Descriptions ...........................................................................................559
18.3.2 Port C Data Register (PCDR) ..............................................................................559
18.4 Port D ................................................................................................................................561
18.4.1 Register Descriptions ...........................................................................................563
18.4.2 Port D Data Registers H and L (PDDRH and PDDRL).......................................563
18.5 Port E ................................................................................................................................566
18.5.1 Register Descriptions ...........................................................................................567
18.5.2 Port E Data Register L (PEDRL) .........................................................................567
18.6 Port F.................................................................................................................................569
18.6.1 Register Descriptions ...........................................................................................569
18.6.2 Port F Data Register (PFDR) ...............................................................................569
Section 19 Flash Memory (F-ZTAT Version) .................................................. 571
19.1 Features .............................................................................................................................571
19.2 Mode Transitions ..............................................................................................................572
19.3 Block Configuration..........................................................................................................576
19.4 Input/Output Pins ..............................................................................................................577
19.5 Register Descriptions ........................................................................................................577
19.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................577
19.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................579
19.5.3 Erase Block Register 1 (EBR1)............................................................................579
19.5.4 Erase Block Register 2 (EBR2)............................................................................580
19.5.5 RAM Emulation Register (RAMER)...................................................................580
19.6 On-Board Programming Modes........................................................................................581
19.6.1 Boot Mode ...........................................................................................................582
19.6.2 Programming/Erasing in User Program Mode.....................................................584
19.7 Flash Memory Emulation in RAM....................................................................................585
19.8 Flash Memory Programming/Erasing ...............................................................................587
19.8.1 Program/Program-Verify Mode...........................................................................587
19.8.2 Erase/Erase-Verify Mode.....................................................................................589
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................589
19.9 Program/Erase Protection .................................................................................................591
Rev. 2.0, 09/02, page xix of xxxviii