SH7144 Datasheet, PDF (439/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Start initialization
Clear RIE, TIE, TEIE, MPIE, TE
and RE bits in SCR to 0.*
Set CKE1 and CKE0 bits in
[1]
SCR to 0. ( TE and RE bits are 0)
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR.
Set data transfer format in
[2]
SMR to 0.
Set value in BRR
[3]
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
Wait
No
1-bit interval elapsed?
Yes
Set RIE, TIE, TEIE, and MPIE
bits in SCR.
[4]
Set PFC to the external pins
(SCK, TXD, and RXD) to be used.
[5]
Set TE or RE bits in SCR to 1. [6]
[4] Set RIE, TIE, TEIE, and MPIE bits in
SCR to 1.
[5] Set PFC for the external pins to be
used. Set RXD input for reception and
TXD output for transmission. Set SCK
input/output according to the value set
by CKE1 and CKE0.
[6] Set TE or RE bit in SCR to 1*. Then,
TXD, RXD, and SCK pins can be used.
The TXD pin is in the mark status at
transmission. If the setting is reception
in clocked synchronous mode and
synchronous clock output (clock
master) at this time, then a clock starts
being output from the SCK pins.
<Transfer start>
Note: In simultaneous transmit and receive operation, the TE and RE bits should both be
cleared to 0 or set to 1 simultaneously.
Figure 13.15 Sample SCI Initialization Flowchart
Rev. 2.0, 09/02, page 399 of 732