SH7144 Datasheet, PDF (757/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Item
Table 11.1 MTU
Functions
Page
192
Revisions (See Manual for Details)
Descriptions added.
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4
PWM mode 2
Ο
Ο
Ο
—
—
Complementary —
—
—
Ο
Ο
PWM mode
Reset PMW
—
—
—
Ο
mode
AC
Ο
—
—
Ο
Ο
synchronous
motor drive
mode
Phase counting —
Ο
Ο
—
—
mode
Table 11.10 TIORH_0
(channel 0) to Table
11.25 TIORL_4
(Channel 4)
205 to
220
Table 11.27 Output
231
Level Select Function
Figure 11.30
259
Procedure for Selecting
the Reset-
Synchronized PWM
Mode
Figure 11.33 Example 264
of Complementary
PWM Mode Setting
Procedure
Pin description amended.
Output prohibited → Output retained
Description added.
Legend:
X: Don’t care
Note: * After power-on reset, 0 is output until TIOR is set.
Bit No. amended.
Bit 1 → Bit 0
Figure amended.
Enable waveform output
PFC setting
Start count operation
[8]
[7] Set bits MD3-MD0 in TMDR_3 to B'1000 to select
the reset-synchronized PWM mode. Do not set to TMDR_4.
[9]
[8] Set the enabling/disabling of the PWM waveform output
pin in TOER.
[10]
[9] Set the port control register and the port I/O register.
Reset-synchronized PWM mode
[10] Set the CST3 bit in the TSTR to 1 to start the count
operation.
Figure amended.
Note: The output waveform starts to toggle operation at the point of
TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty.
Enable waveform output
PFC setting
Start count operation
[10]
[9] Select complementary PWM mode in timer mode register 3
(TMDR_3). Do not set in TMDR_4.
[11] ^{[10] Set enabling/disabling of PWM waveform output pin output in}
the timer output master enable register (TOER).
[11] Set the port control register and the port I/O register.
[12] _{[12] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start}
the count operation.
<Complementary PWM mode>
Rev. 2.0, 09/02, page 717 of 732