SH7144 Datasheet, PDF (526/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Pφ
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 16.4 CMF Set Timing
16.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1 or the clearing
signal after the DTC transfer. Figure 16.5 shows the timing when the CMF bit is cleared by the
CPU.
CMCSR write cycle
T1 T2
Pφ
CMF
Figure 16.5 Timing of CMF Clear by the CPU
Rev. 2.0, 09/02, page 486 of 732