SH7144 Datasheet, PDF (400/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

12.6.5 System Reset by WDTOVF Signal
If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly.
Avoid to connect the WDTOVF signal to the RES input pin directly. To reset the entire system
with the WDTOVF signal, use the circuit shown in figure 12.9.
Reset input
This LSI
Reset signal to entire system
Figure 12.9 Example of System Reset Circuit Using WDTOVF Signal
12.6.6 Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a
TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset.
12.6.7 Manual Reset in Watchdog Timer Mode
When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits
until the end of the bus cycle at the time of manual reset generation before making the transition to
manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a
manual reset occurs while the bus is released, manual reset exception processing will be deferred
until the CPU acquires the bus. However, if the interval from generation of the manual reset until
the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles,
the internal manual reset source is ignored instead of being deferred, and manual reset exception
processing is not executed.
Rev. 2.0, 09/02, page 360 of 732