SH7144 Datasheet, PDF (271/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 11.27 Output Level Select Function
Bit 0
OLSP
0
1
Initial Output
High level
Low level
Active Level
Low level
High level
Function
Compare Match Output
Up Count
Down Count
Low level
High level
High level
Low level
Figure 11.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1,
OLSP = 1.
TCNT_3, and
TCNT_4 values
TGRA_3
TGRA_4
TCNT_3
TCNT_4
TDDR
H'0000
Positive
phase output
Reverse
phase output
Initial
output
Initial
output
Active
level
Compare match
output (up count)
Active level
Compare match
output (up count)
Compare match
output (down count)
Compare match
output (down count)
Active level
Time
Figure 11.2 Complementary PWM Mode Output Level Example
11.3.12 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode.
These register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Rev. 2.0, 09/02, page 231 of 732