SH7144 Datasheet, PDF (402/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Clocked Synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Note: * The description in this section are based on LSB-first transfer.
Figure 13.1 shows a block diagram of the SCI.
Module data bus
Internal
data bus
RxD
TxD
SCK
RDR
RSR
TDR
SSR
BRR
SCR
TSR
SMR
SDCR
Transmission/
reception
control
Baud rate
generator
Parity generation
Clock
Parity check
External clock
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
SDCR: Serial direction control register
Pφ
Pφ/8
Pφ/32
Pφ/128
TEI
TXI
RXI
ERI
Figure 13.1 Block Diagram of SCI
Rev. 2.0, 09/02, page 362 of 732