SH7144 Datasheet, PDF (588/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Register Bit
PECRL1 3
PECRL1 2
PECRL1 1
PECRL1 0
PECRL2 15
PECRL2 14
PECRL2 13
PECRL2 12
PECRL2 11
PECRL2 10
Initial
Bit Name Value R/W
PE9MD1 0
R/W
PE9MD0 0
R/W
PE8MD1 0
R/W
PE8MD0 0
R/W
PE7MD1 0
R/W
PE7MD0 0
R/W
PE6MD1 0
R/W
PE6MD0 0
R/W
PE5MD1 0
R/W
PE5MD0 0
R/W
Description
PE9 Mode
Select the function of the
PE9/TIOC3B/TRST/SCK3 pin. Fixed to TRST
input when using E10A (in DBGMD=H).*
00: PE9 I/O (port)
01: TIOC3B I/O (MTU)
10 Setting prohibited
11: SCK3 I/O (SCI)
PE8 Mode
Select the function of the
PE8/TIOC3A/SCK2/TMS pin. Fixed to TMS input
when using E10A (in DBGMD=H).*
00: PE8 I/O (port)
01: TIOC3A I/O (MTU)
10: SCK2 I/O (SCI)
11: Setting prohibited
PE7 Mode
Select the function of the PE7/TIOC2B/RXD2
pin.
00: PE7 I/O (port)
01: TIOC2B I/O (MTU)
10: RXD2 input (SCI)
11: Setting prohibited
PE6 Mode
Select the function of the
PE6/TIOC2A/SCK3/AUDATA0 pin.
00: PE6 I/O (port)
01: TIOC2A I/O (MTU)
10: SCK3 I/O (SCI)
11: AUDATA0 I/O (AUD)*
PE5 Mode
Select the function of the
PE5/TIOC1B/TXD3/AUDATA1 pin.
00: PE5 I/O (port)
01: TIOC1B I/O (MTU)
10: TXD3 output (SCI)
11: AUDATA1 I/O (AUD)*
Rev. 2.0, 09/02, page 548 of 732