SH7144 Datasheet, PDF (455/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

The TDRE and RDRF flags are set/cleared under the following conditions. The setting of these
flags affects the state of the interrupt flag.
TDRE
0
1
Description
Transmission cannot be started or the next datum for transmission is present in the
ICDR (ICDRT).
(Initial Condition)
[Clearing conditions]
(1) In the transmission mode (TRS = 1), writing of a datum for transmission to ICDR
(ICDRT).
(2) In the I²C bus format or the serial format, detection of the stop condition from the
bus line’s state after the issue of the stop-condition signal.
(3) Detection of the stop condition when the interface is in I²C bus format.
(4) In the receive mode (TRS = 0) (writing of 0 to TRS during transmission is enabled
after reception of a frame that includes the acknowledge bit).
The next datum for transmission can be written to ICDR (ICDRT).
[Setting conditions]
(1) Detection, by the I²C bus format or the serial format in the master mode
(TRS = 1), of the start condition from the bus line’s state after the issue of the
start-condition signal.
(2) Transfer of data from ICDRT to ICDRS (data is transferred from ICDRT to ICDRS
when TRS = 1, TDRE = 0, and ICDRS is empty).
(3) Changing of the mode from reception (TRS = 0) to transmission (TRS = 1) after
detection of the start condition.
RDRF
0
1
Description
The datum in ICDR (ICDRR) is invalid.
(Initial Condition)
[Clearing condition]
When, in the receive mode, data received in ICDR (ICDRR) is read.
The data received in ICDR (ICDRR) can be read.
[Setting condition]
When data is transferred from ICDRS to ICDRR.
When the correct reception of data is allowed by TRS and RDRF both being 0, any
received data is transferred from ICDRS to ICDRR.
Rev. 2.0, 09/02, page 415 of 732