SH7144 Datasheet, PDF (500/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

9. Points for Caution in the Execution of the Instruction that Sets the I²C Bus Interface Stop
Condition
If the rise time in the 9^th cycle of SCL exceeds the specified value due to a high bus-load
capacitance, or if a slave device inserts a wait by setting the level on SCL low, read SCL in the
following way to confirm that the level is low, and then execute the instruction that sets the
stop condition.
SCL
SDA
9^th cycle
VIH
Period for securing
the high-level period
SCL is detected as low
since this waveform takes
a long time to rise.
IRIC
Stop condition
[1] Decision on whether [2] Execution of the instruction
or not SCL is low
that sets the Stop Condition
Figure 14.20 Timing for the Setting of the Stop Condition
10. Set the HNDS bit in serial control register X (SCRX) to 1.
11. In slave transmit operation of the I²C bus interface module, when ICDR is read from or ICCR
is read from or written to at the moment address reception is switched to data transmission,
erroneous data may be transmitted.
In normal transmit operation, when a first frame is received and the received address matches,
the TRS bit is automatically set to 1 and transmit mode is entered if the R/W bit of the 8th
clock cycle is 1. The SCL pin is then fixed to low from the fall of the 9th clock of the first
frame until the transmit data is written to the ICDR register.
However, when ICDR is read from or ICCR is read from or written to within 6 peripheral
clock cycles (half-tone dot-meshing area in figure 14.21) after the rising edge of the 9th
transmit/receive clock for address reception of the first frame, the SCL pin is not fixed low
after the fall of the 9th clock for the first frame. The master device starts sending clock signals
before the slave device has written transmit data to ICDR. As a result, data in the ICDR shift
register is output to the SDA pin, and erroneous data is transmitted to the master device.
Rev. 2.0, 09/02, page 460 of 732