SH7144 Datasheet, PDF (127/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

6.8 Data Transfer with Interrupt Request Signals
The following data transfers can be done using interrupt request signals:
• Activate DMAC only, CPU interrupts do not occur
• Activate DTC only, CPU interrupts according to DTC settings
Interrupt sources that are activated by DMAC are masked without being input to INTC. Mask
condition is as follows:
Mask condition = DME • (DE0 • interrupt source select0 + DE1 • interrupt source select1 + DE2
• interrupt source select2 + DE3 • interrupt source select3)
The INTC masks CPU interrupts when the corresponding DTE bit is 1. The conditions for clearing
DTE and interrupt source flag are listed below.
DTE clear condition = DTC transfer end • DTECLR
Interrupt source flag clear condition = DTC transfer end • DTECLR+DMAC transfer end
Where: DTECLR = DISEL + counter 0.
Figure 6.6 shows a control block diagram.
Interrupt source
Interrupt source
Flag clear (by DMAC)
Interrupt source
flag clear (by DTC)
DMAC
Interrupt source
(not designated as DMAC activation source)
DTER
DTE clear
CPU interrupt request
DTC activation
request
DTECLR
Transfer end
Figure 6.6 Interrupt Control Block Diagram
Rev. 2.0, 09/02, page 87 of 732