SH7144 Datasheet, PDF (382/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
Bit Name Initial value R/W Description
8
PIE
0
R/W Port Interrupt Enable
This bit enables/disables interrupt requests when any
of the POE0F to POE3F bits of the ICSR1 are set to 1
0: Interrupt requests disabled
1: Interrupt requests enabled
7
POE3M1 0
R/W POE3 mode 1, 0
6
POE3M0 0
R/W These bits select the input mode of the POE3 pin
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been
sampled for 16 Pφ/8 clock pulses, and all are low
level.
10: Accept request when POE3 input has been
sampled for 16 Pφ/16 clock pulses, and all are
low level.
11: Accept request when POE3 input has been
sampled for 16 Pφ/128 clock pulses, and all are
low level.
5
POE2M1 0
R/W POE2 mode 1, 0
4
POE2M0 0
R/W These bits select the input mode of the POE2 pin
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been
sampled for 16 Pφ/8 clock pulses, and all are low
level.
10: Accept request when POE2 input has been
sampled for 16 Pφ/16 clock pulses, and all are
low level.
11: Accept request when POE2 input has been
sampled for 16 Pφ/128 clock pulses, and all are
low level.
Rev. 2.0, 09/02, page 342 of 732