SH7144 Datasheet, PDF (183/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

CK
Address
T1
T2
Tidle
T1
T2
Data
CSn space read
Idle cycles
CSm space write
Figure 9.7 Example of Idle Cycle Insertion
Bits IW31 and IW30 in BCR2 specify the number of idle cycles inserted in the case of a write
cycle to CS3 space or an access to different space after CS3 space read.
Bits IW21 and IW20 specify the number of idle cycles inserted for a CS2 space, bits IW11 and
IW10 specify for a CS1 space, and bits IW01 and IW00 specify for a CS0 space, respectively.
9.7.2 Simplification of Bus Cycle Start Detection
For consecutive accesses to the same CS space, waits are inserted to provide the number of idle
cycles designated by bits CW3 to CW0 in BCR2. However, in the case of a write cycle after a
read, the number of idle cycles inserted will be the larger of the two values designated by the IW
and CW bits. When idle cycles already exist between access cycles, waits are not inserted.
Figure 9.8 shows an example. A continuous access idle is specified for CSn space, and CSn space
is consecutively write-accessed.
Rev. 2.0, 09/02, page 143 of 732