82801BA Datasheet, PDF (98/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.5.13 DMA Request Deassertion
An end of transfer is communicated to the ICH2 through a special SYNC field transmitted by the
peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting
LDREQ#. If a DMA transfer is several bytes (e.g., a transfer from a demand mode device), the
ICH2 needs to know when to deassert the DMA request based on the data currently being
transferred.
The DMA agent uses a SYNC encoding on each byte of data being transferred which indicates to
the ICH2 whether this is the last byte of transfer or if more bytes are requested. To indicate the last
byte of transfer, the peripheral uses a SYNC value of 0000b (ready with no error), or ‘1010b’
(ready with error). These encodings tell the ICH2 that this is the last piece of data transferred on a
DMA read (ICH2 to peripheral), or the byte which follows is the last piece of data transferred on a
DMA write (peripheral to ICH2).
When the ICH2 sees one of these two encodings, it ends the DMA transfer after this byte and
deasserts the DMA request to the 8237. Therefore, if the ICH2 indicated a 16 bit transfer, the
peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. The
ICH2 will not attempt to transfer the second byte, and will deassert the DMA request internally.
If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the indicated size,
then the ICH2 will only deassert the DMA request to the 8237 since it does not need to end the
transfer.
If the peripheral wishes to keep the DMA request active, it uses a SYNC value of 1001b (ready
plus more data). This indicates to the 8237 that more data bytes are requested after the current byte
has been transferred; the ICH2 keeps the DMA request active to the 8237. Therefore, on an 8-bit
transfer size, if the peripheral indicates a SYNC value of 1001b to the ICH2, the data will be
transferred and the DMA request remains active to the 8237. At a later time, the ICH2 will then
come back with another START - CYCTYPE - CHANNEL - SIZE etc. combination to initiate
another transfer to the peripheral.
The peripheral must not assume that the next START indication from the ICH2 is another grant to
the peripheral if it had indicated a SYNC value of 1001b. On a single mode DMA device, the 8237
re-arbitrates after every transfer. Only demand mode DMA devices can be guaranteed that they will
receive the next START indication from the ICH2.
Note: Indicating a 0000b or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit channel (first
byte of a 16 bit transfer) is an error condition.
Note: The host stops the transfer on the LPC bus as indicated, fill the upper byte with random data on
DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred,
incrementing the 8237’s address and decrementing its byte count.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet