82801BA Datasheet, PDF (265/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.1.3
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
04–05h
000Fh
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
SERR# Enable (SERR_EN)—R/W.
1 = Enable. Allow SERR# to be generated.
0 = Disable.
Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
1 = The ICH will take normal action when a parity error is detected.
0 = No action is taken when detecting a parity error.
VGA Palette Snoop (VPS)—RO. Hardwired to 0
Postable Memory Write Enable (PMWE)—RO. Hardwired to 0
Special Cycle Enable (SCE). Hardwired to 1.
Bus Master Enable (BME)—RO. Hardwired to 1 to indicate that bus mastering can not be disabled
for function 0 (DMA/ISA Master).
Memory Space Enable (MSE)—RO. Hardwired to 1 to indicate that memory space can not be
disabled for Function 0 (LPC I/F).
I/O Space Enable (IOE)—RO. Hardwired to 1 to indicate that the I/O space cannot be disabled for
function 0 (LPC I/F).
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-3