82801BA Datasheet, PDF (480/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

I/O Register Index
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name
Master PIC ICW2 Init. Cmd Word 2
Register
Master PIC ICW3 Init. Cmd Word 3
Register
Master PIC ICW4 Init. Cmd Word 4
Register
Master PIC OCW1 Op Ctrl Word 1
Register
Aliased at 20h–21h
Aliased at 20h–21h
Aliased at 20h–21h
Aliased at 20h–21h
Aliased at 20h–21h
Aliased at 20h–21h
Aliased at 20h–21h
Aliased at 20h–21h
Counter 0 Interval Time Status Byte
Format
Counter 0 Counter Access Port
Register
Counter 1 Interval Time Status Byte
Format
Counter 1 Counter Access Port
Register
Counter 2 Interval Time Status Byte
Format
Counter 2 Counter Access Port
Register
Timer Control Word Register
Timer Control Word Register Read
Back
Counter Latch Command
Aliased at 40h–43h
NMI Status and Control Register
NMI Enable Register
Real-Time Clock (Standard RAM)
Index Register
Real-Time Clock (Standard RAM)
Target Register
Extended RAM Index Register
Extended RAM Target Register
Port
21h
24h–25h
28h–29h
24h–25h
2Ch–2Dh
30h–31h
34h–35h
38h–39h
3Ch–3Dh
40h
41h
42h
43h
50h–53h
61h
70h
70h
EDS Section and Location
Section 9.4.3, “ICW2—Initialization Command Word 2
Register” on page 9-35
Section 9.4.4, “ICW3—Master Controller Initialization
Command Word 3 Register” on page 9-35
Section 9.4.6, “ICW4—Initialization Command Word 4
Register” on page 9-36
Section 9.4.7, “OCW1—Operational Control Word 1
(Interrupt Mask) Register” on page 9-36
Section 9.3.2, “SBYTE_FMT—Interval Timer Status
Byte Format Register” on page 9-32
Section 9.3.3, “Counter Access Ports Register” on
page 9-32
Section 9.3.2, “SBYTE_FMT—Interval Timer Status
Byte Format Register” on page 9-32
Section 9.3.3, “Counter Access Ports Register” on
page 9-32
Section 9.3.2, “SBYTE_FMT—Interval Timer Status
Byte Format Register” on page 9-32
Section 9.3.3, “Counter Access Ports Register” on
page 9-32
Section 9.3.1, “TCW—Timer Control Word Register” on
page 9-30
Section 9.3.1.1, “RDBK_CMD—Read Back Command”
on page 9-31
Section 9.3.1.2, “LTCH_CMD—Counter Latch
Command” on page 9-31
Section 9.7.1, “NMI_SC—NMI Status and Control
Register” on page 9-51
Section 9.7.2, “NMI_EN—NMI Enable (and Real Time
Clock Index)” on page 9-52
Table 9-7 “RTC (Standard) RAM Bank” on page 9-47
Section 9.7.2, “NMI_EN—NMI Enable (and Real Time
Clock Index)” on page 9-52
71h
Table 9-7 “RTC (Standard) RAM Bank” on page 9-47
72h
73h
A-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet