82801BA Datasheet, PDF (349/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.10.1 GPIO Register I/O Address Map
Table 9-13. Registers to Control GPIO
Offset
Mnemonic
Register Name
00–03h
04–07h
08–0Bh
0C–0Fh
10–13h
14–17h
18–1Bh
1C–1Fh
20–2Bh
2C–2Fh
General Registers
GPIO_USE_SEL GPIO Use Select
GP_IO_SEL GPIO Input/Output Select
—
Reserved
GP_LVL
GPIO Level for Input or Output
—
Reserved
Output Control Registers
GPO_TTL
GPO_BLINK
—
GPIO TTL Select
GPIO Blink Enable
Reserved
Input Control Registers
—
GPI_INV
Reserved
GPIO Signal Invert
Default
Access
1A00 3180h
R/W
0000 FFFFh
R/W
00h
RO
1F1F 0000h
R/W
00h
RO
06630000h
RO
00000000h
R/W
0
RO
00000000h
RO
00000000h
R/W
9.10.2
GPIO_USE_SEL—GPIO Use Select Register
Offset Address:
Default Value:
Lockable:
GPIOBASE + 00h
1A003180h
Yes
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Bit
Description
GPIO Use Select (GPIO_USE_SEL)—R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
21,11,
5:0
Note: ICH2 82801BA: Bits 31:29, 26, 15:14, 10:9 and 7 are not implemented because there is no
corresponding GPIO.
ICH2-M 82801BAM: Bits 31:29, 26, 24:22, 20:18, 15:14, 10:9, and 7:6 are not implemented
because there is no corresponding GPIO.
Note: ICH2 82801BA: Bits 28:27, 25:22, 20:18,13:12, 8 and 6 are not implemented because the
corresponding GPIOs are not multiplexed.
ICH2-M 82801BAM: Bits 28:27, 25, 13:12 and 8 are not implemented because the
corresponding GPIOs are not mutiplexed.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-87