82801BA Datasheet, PDF (260/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.26
CNF—ICH2 Configuration Register (HUB-PCI—D30:F0)
Offset Address: 50–51h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:10
9
8
7:3
2
1
0
Reserved.
HP_PCI_EN—R/W. High Priority PCI Enable.
1 = Enables a mode where the REQ[0]#/GNT[0]# signal pair has a higher arbitration priority.
0 = All PCI REQ#/GNT pairs have the same arbitration priority.
Hole Enable (15 MB–16 MB)—R/W.
1 = Enables the 15 MB to 16 MB hole in the DRAM.
0 = Disable
Reserved.
Discard Timer Mode. This bit shortens all of the Delayed Transaction discard timers to 128 PCI
clocks. It controls how long the ICH2-M will wait before flushing previously requested prefetched
read data due to a Delayed Transaction, and then servicing a different request.
0 = 1024 PCI clocks (32 us) (Default).
1 = 128 PCI clocks (4 us).
32-Clock Retry Enable—R/W. System BIOS must set this bit for PCI compliance.
1 = When a PCI device is running a locked memory read cycle, while all other bus masters are
waiting to run locked cycles, concurrent with a LPC DMA transfer, this bit, when set allows the
ICH2 to retry the locked memory read cycle.
0 = If this bit is not set, under the same circumstance, the bus will not be released since all other
masters see the lock in use.
Reserved.
8.1.27 MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0)
Offset Address: 70h
Default Value: 20h
Attribute:
Size:
R/W
8 bits
MTT is an 8-bit register that controls the amount of time that the ICH2’s arbiter allows a PCI
initiator to perform multiple back-to-back transactions on the PCI bus. The ICH2’s MTT
mechanism is used to guarantee a fair share of the Primary PCI bandwidth to an initiator that
performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence
it can not use long burst transfers).
The number of clocks programmed in the MTT represents the guaranteed time slice (measured in
PCI clocks) allotted to the current agent, after which the arbiter grants another agent that is
requesting the bus. The MTT value must be programmed with 8 clock granularity in the same
manner as MLT. For example, if the MTT is programmed to 18h, the selected value corresponds to
the time period of 24 PCI clocks.The default value of MTT is 20h (32 PCI clocks).
Note:
Programming the MTT to a value of 00h disables this function, which could cause starvation issues
for some PCI master devices. Programming of the MTT to anything less than 16 clocks will not
allow the Grant-to-FRAME# latency to be 16 clocks. The MTT timer will time-out before the
Grant-to-FRAME# trigger causing a re-arbitration.
Bit
Description
Multi-Transaction Timer Count Value—R/W. This field specifies the amount of time that grant
7:3 remains asserted to a master continuously asserting its request for multiple transfers. This field
specifies the count in an 8-clock (PCI clock) granularity.
2:0 Reserved.
8-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet