82801BA Datasheet, PDF (262/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.30
ERR_STS—Error Status Register (HUB-PCI—D30:F0)
Offset Address: 92h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
This register records the cause of system errors in Device 30. The actual assertion of SERR# is
enabled via the PCI Command register.
Bit
Description
7:3 Reserved.
SERR# Due to Received Target Abort (SERR_RTA)—R/W.
1 = The ICH2 sets this bit when the ICH2 receives a target abort. If SERR_EN, the ICH2 will also
2
generate an SERR# when SERR_RTA is set.
0 = This bit is cleared by writing a 1.
SERR# Due to Delayed Transaction Time-out (SERR_DTT)—R/W.
1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH2
1
clears the delayed transaction, and sets this bit. If both SERR_DTT_EN and SERR_EN are
set, then ICH2 will also generate an SERR# when SERR_DTT is set.
0 = This bit is cleared by writing a 1.
0 Reserved.
8-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet