82801BA Datasheet, PDF (209/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Output Slot 5: Modem Codec
Output frame slot 5 contains modem DAC data. The modem DAC output supports 16 bit
resolution. At boot time, if the modem codec is supported, the AC’97 controller driver determines
the DAC resolution. During normal runtime operation the ICH2 stuffs trailing bit positions within
this time slot with 0s.
Output Slot 6: PCM Playback Center Front Channel
When set up for 6 channel mode, this slot is used for the front center channel. The format is the
same as Slots 3. If not set up for 6 channel mode, this channel will always be stuffed with 0s by
ICH2.
Output Slots 7–8: PCM Playback Left and Right Rear Channels
When set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear Left and Right channels.
The format for these two channels are the same as Slots 3 and 4.
Output Slot 9: Playback SubWoofer Channel
When set for 6 channel mode, this slot is used for the SubWoofer. The format is the same as Slots 3.
If not set up for 6 channel mode, this channel will always be stuffed with 0s by ICH2.
Output Slots 10–11: Reserved
Output frame slots 10–11 are reserved and are always stuffed with 0s by the ICH2 AC’97
controller.
Output Slot 12: I/O Control
The 16 bits of DAA and GPIO control (output) and status (input) have been directly assigned to
bits on slot 12 to minimize latency of access to changing conditions.
The value of the bits in this slot are the values written to the GPIO control register at offset 54h and
D4h (in the case of a secondary codec) in the modem codec I/O space. The following rules govern
the usage of slot 12.
1. Slot 12 is marked invalid by default on coming out of AC-link reset and will remain invalid
until a register write to 54h/D4h.
2. A write to offset 54h/D4h in codec I/O space will cause the write data to be transmitted on slot
12 in the next frame, with slot 12 marked valid, and the address/data information to also be
transmitted on slots 1 and 2.
3. After the first write to offset 54h/D4h, slot 12 remains valid for all following frames. The data
transmitted on slot 12 is the data last written to offset 54h/D4h. Any subsequent write to the
register will cause the new data to be sent out on the next frame.
4. Slot 12 will get invalidated after the following events: PCI reset, AC'97 cold reset, warm reset,
and hence a wake from S3, S4, or S5. Slot 12 will remain invalid until the next write to offset
54h/D4h.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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