82801BA Datasheet, PDF (255/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.14
8.1.15
IOBASE—I/O Base Register (HUB-PCI—D30:F0)
Offset Address: 1Ch
Default Value: F0h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4
I/O Address Base bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4 KB
alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface to PCI
3:0 bridge does not support 32-bit I/O addressing. This means that the I/O Base Register and I/O Limit
Upper Address registers must be read only.
IOLIM—I/O Limit Register (HUB-PCI—D30:F0)
Offset Address: 1Dh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4
I/O Address Limit bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4 KB
alignment. Bits 11:0 are assumed to be padded to FFFh.
I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface-to-PCI
3:0 bridge does not support 32-bit I/O addressing. This means that the I/O Base Register and I/O Limit
Upper Address registers must be read only.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-7