82801BA Datasheet, PDF (217/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.19.2 Protocol
The FWH Memory cycles use a sequence of events that start with a START field (LFRAME#
active with appropriate AD[3:0] combination) and end with the data transfer. The following
sections describe the cycles in detail.
Preamble
The initiation of the FWH Memory cycles is shown in Figure 5-25. The FWH Memory transaction
begins with LFRAME# going low and a START field driven on AD[3:0]. For FWH Memory Read
cycles, the START field must be ‘1101b’; for FWH Memory Write cycles, the START field must be
‘1110b’. Following the START field is the IDSEL field. This field acts like a chip select in that it
indicates which device should respond to the current transaction. The next seven clocks are the 28-
bit address from where to begin reading in the selected device. Next, an MSIZE value of 0
indicates the master is requesting a single byte.
Figure 5-25. FWH Memory Cycle Preamble
T1
CLK
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11
FRAME#
AD[3:0]
START IDSEL
28 Bit Address
MSIZE
Read Cycle (Single Byte)
For read cycles, after the pre-amble (described above), the host drives a TAR field to give
ownership of the bus to the FWH. After the second clock of the TAR phase, the target device
assumes the bus and begins driving SYNC values. When it is ready, it drives the low nibble, then
the high nibble of data, followed by a TAR to give control back to the host.
Figure 5-26. Single Byte Read
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CLK
FRAME#
AD[3:0]
Preamble
TAR
SYNC
D_Lo D_Hi
TAR
fh d
Figure 5-26 shows a device that requires 3 SYNC clocks to access data. Since the access time can
begin once the address phase has been completed, the two clocks of the TAR phase can be
considered as part of the access time of the part. For example, a device with a 120 ns access time
could assert ‘0101b’ for clocks 1 and 2 of the SYNC phase and ‘0000b’ for the last clock of the
SYNC phase. This would be equivalent to 5 clocks worth of access time if the device started that
access at the conclusion of the Preamble phase. Once SYNC is achieved, the device returns the
data in two clocks and gives ownership of the bus back to the host with a TAR phase.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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