82801BA Datasheet, PDF (377/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

USB Controller Registers
11.2.2
USBSTA—USB Status Register
I/O Offset:
Default Value:
Base + (02–03h)
0020h
Attribute:
Size:
R/WC
16 bits
This register indicates pending interrupts and various states of the Host Controller. The status
resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0
in this register by writing a 1 to it.
Bit
Description
15:6 Reserved.
HCHalted—R/WC.
1 = The Host Controller has stopped executing as a result of the Run/Stop bit being set to 0, either
5
by software or by the Host Controller hardware (debug mode or an internal error). Default.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
Host Controller Process Error—R/WC.
1 = The Host Controller has detected a fatal error. This indicates that the Host Controller suffered
a consistency check failure while processing a Transfer Descriptor. An example of a
consistency check failure would be finding an illegal PID field while processing the packet
4
header portion of the TD. When this error occurs, the Host Controller clears the Run/Stop bit
in the Command register to prevent further schedule execution. A hardware interrupt is
generated to the system.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
Host System Error—R/WC.
1 = A serious error occurred during a host system access involving the Host Controller module. In
a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and
3
PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the
Command register to prevent further execution of the scheduled TDs. A hardware interrupt is
generated to the system.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
Resume Detect (RSM_DET)—R/WC.
1 = The Host Controller received a “RESUME” signal from a USB device. This is only valid if the
2
Host Controller is in a global suspend state (bit 3 of Command register = 1).
0 = Software resets this bit to 0 by writing a 1 to the bit position.
USB Error Interrupt—R/WC.
1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow).
1
If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0
are set.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
USB Interrupt (USBINT)—R/WC.
1 = The Host Controller sets this bit when the cause of an interrupt is a completion of a USB
transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is
0
detected (actual length field in TD is less than maximum length field in TD), and short packet
detection is enabled in that TD.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
11-11