82801BA Datasheet, PDF (210/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
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AC-link Input Frame (SDIN)
There are two SDIN lines on the ICH2 for use with a primary and secondary codec. Each SDIN pin
can have a codec attached. Depending upon which codec (AC, MC, or AMC) is attached, various
slots will be valid or invalid. The data slots on the two inputs must be completely orthogonal
(except for the tag slot 0), that is, no two data slots at the same location will be valid on both lines.
This precludes the use of two similar codecs (e.g., two ACs or MCs) which use the same time slots.
The input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC’97 controller. As in the case for the output frame, each AC-link input frame
consists of twelve time slots.
A new audio input frame begins with a low-to-high transition of AC_SYNC. AC_SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of
BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of
BIT_CLK, the codec transitions SDIN into the first bit position of slot 0 (codec ready bit). Each
new bit position is presented to AC-link on a rising edge of BIT_CLK and subsequently sampled
by the ICH2 on the following falling edge of BIT_CLK. This sequence ensures that data transitions
and subsequent sample points for both incoming and outgoing data streams are time aligned.
SDIN data stream must follow the AC’97 specification and be MSB justified with all non-valid bit
positions (for assigned and/or unassigned time slots) stuffed with zeros. SDIN data is sampled by
the ICH2 on the falling edge of BIT_CLK.
Input Slot 0: Tag Phase
Input slot 0 consists of a codec ready bit (bit 15) and slot valid bits for each subsequent slot in the
frame (bits [14:3]).
The codec ready bit within slot 0 (bit 15) indicates whether the codec on the AC-link is ready for
operation. If the codec ready bit in slot 0 is a zero, the codec is not ready for normal operation.
When the AC-link codec ready bit is a 1, it indicates that the AC-link and codec control and status
registers are in a fully operational state. The codec ready bits are visible through the Global Status
register of the ICH2. Software must further probe the Powerdown Control/Status register in the
codec to determine exactly which subsections, if any, are ready.
Bits [14:3] in slot 0 indicate which slots of the input stream to the ICH2 contain valid data, just as
in the output frame. The remaining bits in this slot are stuffed with zeros.
Input Slot 1: Status Address Port / Slot Request Bits
The status port is used to monitor status of codec functions including, but not limited to, mixer
settings and power management.
Slot 1 must echo the control register index, for historical reference, for the data to be returned in
slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in slot 0.
For multiple sample rate output, the codec examines its sample rate control registers, the state of its
FIFOs, and the incoming SDOUT tag bits at the beginning of each audio output frame to determine
which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current audio input
frame signal which output slots require data from the controller in the next audio output frame. For
fixed 48 kHz operation the SLOTREQ bits are always set active (low) and a sample is transferred
each frame.
For multiple sample rate input, the tag bit for each input slot indicates whether valid data is present
or not.
82801BA ICH2 and 82801BAM ICH2-M Datasheet