82801BA Datasheet, PDF (365/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.2 Bus Master IDE I/O Registers (D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located
in Device 31:Function 1 Configuration space (offset 20h). All bus master IDE I/O space registers
can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an
indeterminate, inconsistent value; writes to reserved bits have no affect (but should not be
attempted). The description of the I/O registers is shown in Table 10-2.
Table 10-2. Bus Master IDE I/O Registers
Offset
00h
01h
02h
03h
04h–07h
08h
09h
0Ah
0Bh
0Ch–0Fh
Mnemonic
BMICP
BMISP
BMIDP
BMICS
BMISS
BMIDS
Register
Command Register Primary
Reserved
Status Register Primary
Reserved
Descriptor Table Pointer Primary
Command Register Secondary
Reserved
Status Register Secondary
Reserved
Descriptor Table Pointer Secondary
Default
00h
00h
00h
00h
xxxxxxxxh
00h
00h
00h
00h
xxxxxxxxh
Type
R/W
RO
R/WC
RO
R/W
R/W
RO
R/WC
RO
R/W
10.2.1
BMIC[P,S]—Bus Master IDE Command Register
Address Offset:
Default Value:
Primary: 00h
Secondary: 08h
00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved. Returns 0s.
Read / Write Control (RWC)—R/W. This bit sets the direction of the bus master transfer: This bit
must NOT be changed when the bus master function is active.
3
0 = Memory reads.
1 = Memory writes
2:1 Reserved. Returns 0s.
Start/Stop Bus Master (START)—R/W.
1 = Enables bus master operation of the controller. Bus master operation begins when this bit is
detected changing from a zero to a one. The controller will transfer data between the IDE device
and memory only when this bit is set. Master operation can be halted by writing a '0' to this bit.
0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped
and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master
0
IDE Active bit of the Bus Master IDE Status register for that IDE channel is set) and the drive has
not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that
IDE channel is not set), the bus master command is said to be aborted and data transferred from
the drive may be discarded instead of being written to system memory.
This bit is intended to be reset after the data transfer is completed, as indicated by either the Bus
Master IDE Active bit or the Interrupt bit of the Bus Master IDE Status register for that IDE
channel being set, or both.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-11