82801BA Datasheet, PDF (131/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Both processors must immediately respond to the STPCLK# assertion with stop grant
acknowledge cycles before the 82801BA ICH2 asserts CPUSLP# to meet the processor setup time
for CPUSLP#. Meeting the processor setup time for CPUSLP# is not an issue if both processors
are idle when the system is entering S1. If it cannot be guaranteed that both processors will be idle,
the SLP_EN bit must not be enabled. Note that setting SLP_EN to 1 is not required to support S1
in a dual-processor configuration.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state and thus,
STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose
power. Upon exit from those states, the processors will have their power restored.
5.11.3 Speed Strapping for Processor
The ICH2 directly sets the speed straps for the processor, saving the external logic that has been
needed with prior PCIsets. Refer to the processor specification for speed strapping definition. The
ICH2 performs the following to set the speed straps for the processor:
1. While PWROK is active, the ICH2 drives A20M#, IGNNE#, NMI, and INTR high.
2. As soon as PWROK goes active, the ICH2 reads the FREQ_STRAP field contents.
3. The next step depends on the power state being exited as described in Table 5-34.
Table 5-34. Frequency Strap Behavior Based on Exit State
State
Exiting
ICH2
S1
There is no processor reset, so no frequency strap logic is used.
S3, S4, S5,
or G3
Based on PWROK going active, the ICH2 deasserts PCIRST#, and based on the value of the
FREQ_STRAP field (D31:F0,Offset D4), the ICH2 drives the intended core frequency values on
A20M#, IGNNE#, NMI, and INTR. The ICH2 holds these signals for 120 ns after CPURST# is
deasserted by the Host controller.
Table 5-35. Frequency Strap Bit Mapping
FREQ_STRAP bits [3:0]
3
2
1
0
Sets High/Low Level for the Corresponding Signal
NMI
INTR
IGNNE#
A20M#
NOTE: The FREQ_STRAP register is in the RTC well. The value in the register can be forced to 1111 via a
pinstrap (AC_SDOUT signal), or the ICH2 can automatically force the speed strapping to 1111 if the
processor fails to boot.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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