82801BA Datasheet, PDF (193/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.17.1.1 Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to determine the
progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the
command completes successfully, the INTR bit is set in the Host Status Register. If the device does
not respond with an acknowledge and the transaction times out, the DEV_ERR bit is set. If
software sets the KILL bit in the Host Control Register while the command is running, the
transaction will stop and the FAILED bit will be set.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent. The format
of the protocol is shown in Table 5-76.
Table 5-76. Quick Protocol
Bit
Description
1
Start Condition
2:8
Slave Address - 7 bits
9
Read / Write Direction
10
Acknowledge from slave
11
Stop
Send Byte / Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent
For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is
stored in the DATA0 register.
The Receive Byte is similar to a Send Byte; the only difference is the direction of data transfer. The
format of the protocol is shown in Table 5-77.
Table 5-77. Send / Receive Byte Protocol
Send Byte Protocol
Bit
1
2:8
9
10
11:18
19
20
Description
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
Receive Byte Protocol
Description
Start
Slave Address - 7 bits
Read
Acknowledge from slave
Data byte from slave
NOT Acknowledge
Stop
Write Byte/Word
The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data
to be written. When programmed for a write byte/word command, the Transmit Slave Address,
Device Command and Data0 Registers are sent. In addition, the Data1 Register is sent on a write
word command. The format of the protocol is shown in Table 5-78.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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