82801BA Datasheet, PDF (352/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.10.5
GPO_BLINK—GPO Blink Enable Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +18h
0004 0000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
See bit description
Bit
31:29, 26, 24:20,
17:0
(ICH2)
31:29, 26, 24:20,
18:0
(ICH2-M)
28:27, 25
19:18 (ICH2)
19 (ICH2-M)
Description
Reserved
GPIO Blink (GP_BLINK[n])—R/W. The setting of these bits will have no effect if the
corresponding GPIO is programmed as an input. These bits correspond to GPIO that
are in the Resume well and will be reset to their default values by RSMRST# but not by
PCIRST#.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink
at a rate of approximately once per second. The high and low times have
approximately 50% duty cycle. The GP_LVL bit is not altered when this bit is set.
GPIO Blink (GP_BLINK[n])—R/W. The setting of these bits will have no effect if the
corresponding GPIO is programmed as an input. These bits correspond to GPIO that
are in the Core well, and will be reset to their default values by PCIRST#.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink
at a rate of approximately once per second. The high and low times have
approximately 50% duty cycle. The GP_LVL bit is not altered when this bit is set.
NOTES:.
1. ICH2 82801BA: GPIO[18] blinks, by default, immediately after reset. This signal could be
connected to an LED to indicate a failed boot (by programming BIOS to clear GP_BLINK[18]
after successful POST).
9-90
82801BA ICH2 and 82801BAM ICH2-M Datasheet