82801BA Datasheet, PDF (165/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
6. The controller transfers data to/from memory responding to DMA requests from the IDE
device. The IDE device and the host controller may or may not throttle the transfer several
times. When the last data transfer for a region has been completed on the IDE interface, the
next descriptor is fetched from the table. The descriptor contents are loaded into the Current
Base and Current Count registers.
7. At the end of the transfer the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then
reads the controller status followed by the drive status to determine if the transfer completed
successfully.
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers
terminate when the physical region described by the last PRD in the table has been completely
transferred. The active bit in the Status Register is reset and the DDRQ signal masked.
The buffer is flushed (when in the write state) or invalidated (when in the read state) when a
terminal count condition exists (i.e., the current region descriptor has the EOL bit set and that
region has been exhausted). The buffer is also flushed (write state) or invalidated (read state) when
the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register
and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, can be assured
that all data destined for system memory has been transferred and that data is valid in system
memory. Table 5-54 describes how to interpret the Interrupt and Active bits in the Status Register
after a DMA transfer has started.
During concurrent DMA or Ultra ATA transfers, the ICH2 IDE interface arbitrates between the
primary and secondary IDE cables when a PRD expires.
Table 5-54. Interrupt/Active Bit Interaction Definition
Interrupt
0
1
1
0
Active
Description
1
DMA transfer is in progress. No interrupt has been generated by the IDE device.
The IDE device generated an interrupt. The controller exhausted the Physical
0
Region Descriptors. This is the normal completion case where the size of the
physical memory regions was equal to the IDE device transfer size.
The IDE device generated an interrupt. The controller has not reached the end of the
1
physical memory regions. This is a valid completion case where the size of the
physical memory regions was larger than the IDE device transfer size.
This bit combination signals an error condition. If the Error bit in the status register is
0
set, then the controller has some problem transferring data to/from memory.
Specifics of the error have to be determined using bus-specific information. If the
Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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