82801BA Datasheet, PDF (168/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Operation
Initial setup programming consists of enabling and performing the proper configuration of ICH2
and the IDE device for Ultra ATA/33 operation. For ICH2, this consists of enabling Synchronous
DMA mode and setting up appropriate Synchronous DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is
followed. Once programmed, the drive and ICH2 control the transfer of data via the Ultra ATA/33
protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase,
and a burst termination phase.
The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the
transfer, the ICH2 asserts the DMACK# signal. When DMACK# signal is asserted, the host
controller drives CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the ICH2 deasserts
STOP, waits for the IDE device to assert DMARDY#, and then drives the first data word and
STROBE signal. For read cycles, the ICH2 tri-states the DD lines, deasserts STOP, and asserts
DMARDY#. The IDE device then sends the first data word and STROBE.
The data transfer phase continues the burst transfers with the data transmitter (ICH2 - writes, IDE
device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on
each rising and falling edge of STROBE. The transmitter can pause the burst by holding STROBE
high or low, resuming the burst by again toggling STROBE. The receiver can pause the burst by
deasserting DMARDY# and resumes the transfers by asserting DMARDY#. The ICH2 pauses a
burst transaction to prevent an internal line buffer over or under flow condition, resuming once the
condition has cleared. It may also pause a transaction if the current PRD byte count has expired,
resuming once it has fetched the next PRD.
The current burst can be terminated by either the transmitter or receiver. A burst termination
consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The ICH2 can stop a burst
by asserting STOP; the IDE device acknowledges by deasserting DMARQ. The IDE device stops a
burst by deasserting DMARQ and the ICH2 acknowledges by asserting STOP. The transmitter then
drives the STROBE signal to a high level. The ICH2 then drives the CRC value on the DD lines
and deasserts DMACK#. The IDE device latches the CRC value on the rising edge of DMACK#.
The ICH2 terminates a burst transfer if it needs to service the opposite IDE channel, if a
Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon
transferring the last data from the final PRD.
CRC Calculation
Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33 transfers. The
CRC value is calculated for all data by both the ICH2 and the IDE device over the duration of the
Ultra ATA/33 burst transfer segment. This segment is defined as all data transferred with a valid
STROBE edge from DDACK# assertion to DDACK# deassertion. At the end of the transfer burst
segment, the ICH2 drives the CRC value onto the DD[15:0] signals. It is then latched by the IDE
device on deassertion of DDACK#. The IDE device compares the ICH2 CRC value to its own and
reports an error if there is a mismatch.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet